CeraLink’s benefit in power module applications

The integration of snubber capacitors or part of the DC-link capacitance into the power module for inverters is a trend that aims towards improving the overall inverter efficiency and performance on the one hand and lowering the system costs on the other. However, due to the harsh conditions inside the power module, only ceramic capacitors can be considered. CeraLink, a high-voltage ceramic capacitor from TDK, which is specially designed for power electronic applications, can offer significant advantages over standard multilayer ceramic capacitors (MLCCs), especially when it comes to fast-switching power module applications using silicon carbide (SiC) or gallium nitride (GaN).

The power inverter is a crucial component in electric vehicles (xEVs), converting the DC power from the car battery into AC power to drive the motor. High efficiency and reliability are essential to maximize the vehicle's range, performance, and lifetime. More and more xEVs operate at high voltages (typically around 800 to 900 V) to improve efficiency and reduce charging times. The inverter must be capable of handling these high voltages safely and reliably. By using advanced power semiconductors like silicon carbide (SiC) or gallium nitride (GaN) transistors, lower losses and higher efficiency can be achieved. Nevertheless, effective cooling solutions are necessary to manage the heat generated during operation due to losses. Innovative designs, such as double-sided cooling structures, help to optimize thermal performance and reduce the overall size and weight of the inverter, which is important for improving vehicle range and handling. Besides efficiency and performance, also solution cost is important since the development and manufacturing of high-performance power inverters is expensive. One of the main cost drivers in the power module is the SiC dies. Consequently, any possibility of operating these components more efficiently or reducing the number of required dies can bring significant cost savings.

Figure 1a: Schematic of a standard inverter topology with the HV supply (e.g. battery), the inverter module, and a conventional DC-link capacitor solution.

 

 

Figure 1b: Schematic of a standard inverter topology with the HV supply (e.g. battery), the inverter module, and a distributed DC-link capacitor solution where a part of the capacitance is moved close to the power module.
 

Figure 1c: Schematic of a standard inverter topology with the HV supply (e.g. battery), the inverter module, and an integrated snubber within the power module.
 

Depending on the inverter topology, modern power inverters for xEV typically require a DC-link capacitance of several hundred microfarads which is usually realized using e.g. metalized polypropylene film capacitors (Figure 1(a)). However, such film capacitors are bulky and the desired placement close to the switches is often not possible. Hence, there is a significant parasitic inductance between the DC-link capacitor and the SiC MOSFETs. In combination with steep switching slopes (high di/dt), this can lead to severe voltage overshoots, even with a well-designed busbar. These overshoots not only put the switches at risk but also increase the overall system EMC, potentially requiring larger and more expensive filters.

Hybrid systems, as shown in Figure 1(b) and (c), utilize the possibility to split the DC-Link capacitance by moving a smaller capacitance portion from the bulk DC-link as close as possible to (or even inside) the power module. This small capacitance portion is usually realized by compact low-inductive capacitors, e.g. ceramic capacitors. 

As these components are physically close to the switching elements, they can help to suppress voltage overshoots which otherwise potentially damage the switches. Commonly referred to as snubbers or decoupling capacitors, they store excessive energy from the parasitic inductance when the transistor is switched off. The same applies to the turn-on when the parasitic capacitances of the transistor must be instantly charged. If a ceramic capacitor is placed next to the switching device in parallel with the bulk DC-link capacitor, it can provide this current. Otherwise, this current must be drawn from the bulk DC-link capacitor with the higher parasitic inductance since it is further away from the switching transistor.

In such hybrid systems, the parasitic inductances (e.g. busbar and the DC-link) in combination with the snubber capacitance can lead to unwanted resonances which is usually referred to as the anti-resonance effect. This effect can lead to high reactive currents, far beyond the actual snubber current, leading to unexpected heating of the snubber capacitor and a drop in efficiency. This problem gets more severe if the anti-resonance frequency is close to the switching frequency or any relevant harmonics. With a not-optimized design, the anti-resonance frequency can be easily in the range of 200 to 400 kHz, which may already coincide with the harmonics of typical switching frequencies, leading to severe ringing. To mitigate this effect, the anti-resonance needs to be shifted towards higher frequencies. This can be achieved by minimizing the busbar inductance (e.g. by keeping the busbar as short as possible) and reducing the snubber capacitance to the lowest acceptable level. Furthermore, damping elements may be required, preferably with a frequency-dependency (e.g. by utilizing the skin effect). For more details, we refer to [1].

Figure 2: Influence of loop inductance on voltage overshoots at the semiconductor. The larger the inductance loop induced by the distance of the capacitor to the switches, the larger the voltage overshoots and vice versa. With a temperature rating of +150 °C, CeraLink can be placed very close to the semiconductors, therefore minimizing the inductance loop.

The next logical step is the integration of the snubber capacitor directly into the power module as shown in Figure 1(c). In this case, the snubbers can be placed as close to the switching elements as possible, which minimizes the overall loop inductance significantly, as indicated in Figure 2. Therefore, they work very efficiently to filter any voltage spikes and since the induced voltage overshoot is proportional to the parasitic inductance, less capacitance might be needed in the end.

But besides numerous advantages, the integration of capacitors into the power module imposes also several challenges. Only multilayer ceramic capacitors (MLCCs) can meet the requirements for energy density, current capability, temperature rating, and compactness. However, based on the employed ceramic material, different classes of MLCCs are available which all have their pros and cons. In the following, we consider three different materials, namely the well-known Class-I and Class-II dielectrics, but also an anti-ferroelectric dielectric which is used in TDK’s CeraLink and is specifically designed for tomorrow’s power electronic applications.

Pitfall DC bias effect, current capability, and temperature rating

The capacitance of Class-II MLCCs (e.g. X7R temperature class) decreases with the applied DC voltage—known as the DC-bias effect and shown in Figure 3 (a). The exemplary MLCC with Class-II dielectric (X7R), which has a voltage rating of 630 V and a nominal capacitance of 1 µF, provides only a fraction of this value at an operating voltage of 400 V, i.e. the capacitance drops by almost 80% of its nominal value due to the DC-bias effect. Furthermore, the capacitance also decreases with temperature as shown in Figure 3(b). Albeit this effect is usually less dominant compared to the DC-bias effect, particularly at elevated DC-bias voltages. Nevertheless, when both DC-bias and temperature effects are considered, the 1 µF turns into only approximately 0.2 µF at the operating point. This fact is crucial for many designs as the capacitance in the application then differs significantly from the expected value.

Figure 3: Capacitance characteristics as a function of (a) DC-bias voltage and (b) temperature for MLCCs with Class-I (C0G) and Class-II (X7R and X7T) dielectric in comparison with CeraLink.

Another drawback of MLCCs with Class-II dielectric is their limited current capability together with their tendency to show thermal runaway when several capacitors are combined in parallel, i.e. the hottest capacitor in the capacitor array tends to get even hotter such that the system becomes thermally and/or electrically unstable.

Finally, MLCCs with Class-II dielectric are usually limited to +125 °C max. device temperature, which might be on the edge for certain power module applications, since the SiC-MOSFET junction temperature can go up to +175 °C easily. When it then comes to lifetime, it makes a huge difference if the capacitor is operated already close to its upper-temperature specification (e.g. +125 °C) as compared to a capacitor that is rated for +150 °C but operated only at +125 °C. As a rule of thumb, the service life doubles with every 10 K temperature drop. Furthermore, challenging processing conditions during module assembly (e.g. high temperatures during reflow soldering) can be prohibitive for some standard capacitors.

On the other hand, the capacitance of MLCCs with Class-I dielectric (e.g. C0G temperature class) does not significantly depend on DC bias or temperature. Furthermore, they can handle high ambient temperatures as well as high operating currents easily. However, their capacitance density is typically low, requiring that several parts are required to achieve significant capacitance. This takes up a significant amount of PCB area and can lead to space issues, as well as increasing the overall loop inductance. Such a solution counteracts the original idea of having a low-inductive circuit.

Why CeraLink is different

Unlike MLCCs with Class-I or Class-II dielectric, CeraLink capacitors are based on lead lanthanum zirconium titanate (PLZT) ceramics offering an increase in capacitance with DC-bias voltage as shown in Figure 3(a). Furthermore, the capacitance increases with temperature up to a certain maximum and then decreases (refer to Figure 4). This effectively eliminates the risk of thermal runaway.

Figure 4: Capacitance characteristics of CeraLink over temperature and different DC-bias voltages. This characteristic prevents thermal runaway, which can occur in MLCCs with class II dielectrics.

Figure 5: ESR characteristics of CeraLink over frequency. This allows CeraLink to handle higher ripple currents at higher temperatures.

Figure 6: ESR characteristics of CeraLink over temperature and different DC-bias voltages. CeraLink works even more efficiently at high temperatures.

In addition, CeraLink performs very efficiently at elevated temperatures without the need for additional cooling. This is, firstly, achieved by the ESR decreasing with both frequency and temperature (see Figures 5 and 6), allowing it to deliver significantly higher currents in hot environment applications such as power modules. Secondly, CeraLink’s maximum temperature specification of +150 °C allows it to be placed very close to the semiconductors, helping to reduce the effects of parasitic inductance (see Figure 2). This can eliminate the need for additional thermal management, thereby lowering system costs, and reducing both the size and weight of the system. All these features render CeraLink very suitable for fast-switching power electronic applications using wide-bandgap technology.

System cost advantage

For easier comparison, we concentrate in this paragraph on common, standard MLCC case sizes like EIA 2220 with soft termination and AEC-Q200 (automotive) qualification. Furthermore, we consider only non-stacked MLCCs, respectively MLCCs without lead frames. Usually for automotive power module inverter applications a larger capacitance in the range of several hundred nanofarads to some microfarads is required. CeraLink can fulfill this request with the LP (Low Profile) and FA (Flex-Assembly) series.
 

To illustrate the total cost of ownership advantage of CeraLink over MLCCs with Class-II dielectric, consider a snubber application requiring some 50 nF at 800 V. A comparative analysis between CeraLink B58043E9563M052 (56 nF/900 V) and two to four MLCCs (both 1000 V) from various manufacturers demonstrates significant differences (Table 1). Due to the DC-bias effect, these MLCCs achieve only 12.6 nF, respectively 25.9 nF at an operating voltage of 800 V, necessitating three to four parallel units, whereas a single CeraLink 2220 component suffices.

Although the per-1000-unit price for CeraLink as offered by large online distributors is about twice as high as for most MLCCs, the snubber solution with CeraLink is more cost-effective for this application at this operating point. This cost advantage becomes even greater when PCB area and assembly costs are added. The bottom line is that CeraLink can save up to 60% of the cost based on the given example. Note also that the cost savings can be even higher if the benefits of having a less overall circuit inductance which allows for faster and harder switching are considered (e.g. cooling concept, less EMC, and cheaper filters).

Conclusion

Unlike conventional MLCCs with Class-II dielectric, the capacitance of CeraLink increases with DC-bias voltage and temperature up to their operating point. This characteristic makes them highly versatile for various power electronic applications. They excel at suppressing voltage peaks, and, thanks to their low equivalent series inductance (ESL), they are perfectly suited for working hand in hand with fast-switching wide-bandgap semiconductors. Their ability to handle high ripple currents due to low equivalent series resistance (ESR) at high frequencies and temperatures further highlights their adaptability. Additionally, their ability to operate at high temperatures allows them to be placed very close to high-power switches, effectively damping voltage spikes during rapid switching events (Table 2).
 

In addition to their functional benefits, CeraLink capacitors can enhance cost-effectiveness by minimizing or even eliminating the need for thermal management or filtering. This reduction in system costs also contributes to a decrease in the size and weight of the final product. CeraLink is available in different voltage and capacitance ranges which fit different customer requirements.

Next steps in module integration

The next evolutional step in terms of power module design would be the use of multilayer ceramic substrate materials such as aluminum nitride (AlN). This new substrate material from TDK enables many architectural benefits and boosts the power module to the next level.

The efficiency of power modules is typically highest when operating close to their limits, resulting in higher operating temperatures. Precise and accurate temperature control is essential to operate at these limits and to prevent the semiconductors in the power modules from overheating. To address the temperature accuracy challenge, TDK developed lead-free and RoHS-compatible SMD NTC thermistors that describe the corresponding R/T characteristic curves of existing non fully RoHS-compatible technologies available on the market, enabling a seamless substitution.

References

[1] Neudecker, M. and Chatterjee, P., Mitigating DC Link Anti-Resonance for WBG-Based Designs; Bodo’s Power Systems; 10/2024, pp. 42-46

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