Our website uses cookies to provide you with the best possible service. More information about the use of cookies on this website and how they can be disabled is available on our information page. With your consent, you confirm that you have read the information about the use of cookies and accept it. Please also note our further information on the subject of data privacy policy.

TDK TDK Electronics · TDK Europe

Analog Behavioral Model for Circuit Simulation (PSpice Network Listing)

The model features the given values from the data sheet, including:

  • DC spark-over voltage
  • Impulse spark-over voltage
  • Gap capacitance
  • Insulation resistance
  • Arc voltage
  • Glow voltage
  • Arc transition current
  • Extinguishing current

[---Image_alt---] Circuit_diagram
Figure 1:

Circuit diagram of the simulation

This diagram shows a basic version of the arrester subcircuit in the PSpice model. The design can be fitted into a library file and used just like any other component in the editor.

[---Image_alt---] Surge_simulation
Figure 2:

Surge simulation

The diagram shows the simulation result of an EPCOS arrester with 90 V DC breakdown voltage. The arrester is placed line-to-ground with a simulated 80 V AC source. At the 4 ms mark, a surge (8/20 µs, 1 kV peak) is applied to the line (green graph at top). It can be seen that the arrester limits the overvoltage to ~180 V (the simulated impulse breakdown voltage). It then enters its arc mode (~20 V) and the surge current is shorted to ground (red graph at bottom). As soon as the follow current drops below a certain level, the arrester extinguishes and its internal resistance immediately returns to its initial very high value (9 ms mark).

Simulation of gas discharge tubes
EPCOS provides network listings for specified arresters upon request. They are set up with ORCAD PSpice 16.3 and can be implemented in almost any Spice simulation program running basic libraries (such as ABM, ANALOG, BREAKOUT and SPECIAL). The very fast switching processes of arresters make the model highly CPU-intensive. When using fast transients (>0.1 kV/µs), the recommended step size for the simulation is 100 ns. Higher values may lead to deviating simulation results. The present design does not consider environmental factors such as heat dissipation and is purely ideal (excluding any variance). It is up to the user to determine the service life of the simulated arrester.